Category: New Features

MicroTESK was presented at the Design and Verification Conference (DVCon Europe) held in Munich, Germany on October 24-25, 2018. We reviewed the tool and demonstrated a new feature that allows automatically generating architecture validation suites. DVCon Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.  

MicroTESK will be presented at RISC-V Summit to be held in Santa Clara, CA on December 3-6, 2018. Join us and learn how the free and open RISC-V architecture is revolutionizing the silicon market and beyond!

The MicroTESK team attended the conference “Computer-Aided Technologies in Applied Mathematics” (ICAM) held in Katun, Altai Region, Russia on June 4-8, 2018. We did two presentations on MicroTESK: Alexander Kamkin. Architecture-Level Microprocessor Verification Based on Formal Specifications; Alexander Protsenko & Andrei Tatarnikov. Automatic Test Template Generation Based on ISA Specifications.

The MicroTESK-for-RISC-V test program generator was demonstrated at the RISC-V Workshop held in Barcelona, Spain on May 7-10, 2018. https://riscv.org/2018/05/risc-v-workshop-in-barcelona-proceedings/ Alexander Kamkin (PM) and Andrei Tatarnikov (Team Lead) participated in the poster/demo session of the workshop. Here are links to the slides and video: Poster slides (pages 41 – 42): https://content.riscv.org/wp-content/uploads/2018/05/Barcelona-Workshop-Poster-Session-Slides.pdf Poster announcement (time 20:32 – 22:07): https://www.youtube.com/watch?v=ylTA63vPHYU The next RISC-V workshop will take place in Chennai on July 18-19, 2018 at the Indian Institute of Technology Madras.

MicroTESK was presented at the Microprocessor/SoC Test, Security & Verification (MTV) held in Austin, TX on December 11-12, 2017. Mikhail Chupilko presented our work on maintaining ISA specifications in MicroTESK test program generator (introducing generic operations and revision constructs to nML specification language). The purpose of MTV is to bring researchers and practitioners from the fields of verification, security and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in security and verification and vice versa. This is the 18th edition of the MTV Workshop, a testament to its success in providing an ideal environment…

MicroTESK for RISC-V was presented at the RISC-V Developers Forum held in Moscow, Russia on December 7, 2017. The event was organized by SOVEL jointly with Syntacore, a Russian company specializing in RISC-V cores.

MicroTESK was presented in Taipei, Taiwan. On November 29, Alexander Kamkin, the MicroTESK PM, gave a lecture on architecture-level microprocessor verification at the National Taiwan University of Science and Technology (Taiwan Tech). He considered evolution of test program generators (TPGs), discussed approaches to TPG development automation, and outlined new trends in the area. On December 1, Andrei Tatarnikov, the MicroTESK Core team lead, made a presentation at the Workshop on RTL and High-Level Testing (WRTLT). His talk was about combining multiple TPG engines in the MicroTESK framework. Taiwan Tech was established in 1974 as the first and the best higher education institution of its kind of technological and vocational education system in Taiwan. WRTLT is to bring researchers and practitioners of VLSI testing from all over the world together to…

We are pleased to announce the first build of MicroTESK for RISC-V. The build has the following properties: nML specifications of 201 instructions (including pseudo ones); no MMU specification; sample test templates. Here is a link to the project: http://forge.ispras.ru/projects/microtesk-riscv

Trying to keep up with the times, we started MicroTESK for RISC-V, an open test program generator for the open instruction set architecture (ISA). Here is a link to the project: http://forge.ispras.ru/projects/microtesk-riscv. The first build is expected on the beginning of December. RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation (http://riscv.org).

We are pleased to inform you that MicroTESK has general support for ARMv8.2-A. The formal specifications have been updated: enhanced memory model with wider virtual and physical addresses (52 bits); 16-bit SIMD instructions and FP instructions; Reliability, Availability, and Serviceability (RAS); Statistical Profiling Extension (SPE). It required 70 new instructions, modification of some older ones, and update of the MMU description. The overall specifications include 1000+ instructions; their volume is almost 20 KLOC. ARMv8.2-A is a 64/32-bit architecture developed by ARM Holdings (arm.com).