Year: 2019

As usual, December was rich in events for our team. We attended three conferences, one in Russia and two in USA, where we presented MicroTESK in general (core and engines), MicroTESK for RISC-V (tools for test program generation and deductive binary code verification), and RISC-V Architecture Verification Suite, so-called RISC-V AVS (a set of test programs generated mostly by MicroTESK): Ivannikov ISP RAS Open Conference (ISPRAS Open) held in Moscow, Russia on December 5-6, 2019Microprocessor Test and Verification Workshop (MTV) held in Austin, TX, USA on December 9-10, 2019RISC-V Summit held in San Jose, CA, USA on December 9-12, 2019 We are full of plans and looking forward to implementing them next year. Happy 2020!

MicroTESK 2.5.0 has been released. What's new? Introduced new internal representation, so-called MIR (Middle-level [or MicroTESK] IR)Redesigned the constraint generator (for mark-based situations)Redesigned the symbolic executor (for binary code analysis)Unified the directives (alignment, data definition, and labels) for .text and .data sectionsEnabled a possibility to define data in .textImplemented new directives: .balign, .p2align, and .optionRefactored the code/data allocation logicImplemented a simple instruction-level coverage tracker (experimental)Introduced a new option --coverage-log for tracking test coverageEnabled a possibility to generate test coverage reports in Aspectrace format Used the QEMU4V 0.3.4 simulator for running tests Download: http://forge.ispras.ru/projects/microtesk/files MicroTESK for * Updated The dependent projects have been updated: MicroTESK for RISC-V (0.1.0)MIcroTESK for MIPS (0.1.0)MicroTESK for PowerPC (0.0.4) Related Links MicroTESK for RISC-V: https://forge.ispras.ru/projects/microtesk-riscv/MicroTESK for MIPS: https://forge.ispras.ru/projects/microtesk-mips64/MicroTESK for PowerPC: https://forge.ispras.ru/projects/microtesk-powerpc/QEMU4V: https://forge.ispras.ru/projects/qemu4v/

MicroTESK for RISC-V 0.0.9 has been released. What’s New? Specifications: Added system registers and the related modes Specifications: Added sample specifications of some vector instructions (consistent with RISC-V "V" Vector Extension Version 0.7.1) Specifications: Fixed bugs in RV64A instructions Specifications: Fixed bugs in RV32{F,D} instructions (FEQ, FLE, and FLT) Test Templates: Added sample test templates for vector instructions Test Templates: Changed structure of directories Test Templates: Fixed a Torture-like template ('synthetics/rvxxx') Tool Functions: Moved branch data generators to TestBase Test and Debug: Test suite uses QEMU4V 0.3.3 MicroTESK for RISC-V 0.0.9 can be downloaded from here. More News We started uploading ready-to-use test programs to github: https://github.com/ispras/riscv-avs Here is the link to MicroTESK’s bug tracker at github: https://github.com/ispras/microtesk

Our research on binary code deductive verification was presented at the Workshop on Design Automation for Understanding Hardware Designs (DUHDe), a part of the Design Automation and Test in Europe Conference (DATE), held in Florence, Italy on March 29, 2019. In this work, MicroTESK is used to specify a target instruction set architecture (ISA) and to extract the symbolic representation of a given binary file. Other tools in use include Frama-C, Jessie, and Why3. To demonstrate the approach, we utilize RISC-V, a free and open ISA.  

What's New? Specification of address translation (Sv32, Sv39, and Sv48) Demo templates for address translation Test suite based on QEMU4V 0.3.2 MicroTESK for RISC-V 0.0.8 can be downloaded from here.

MicroTESK 2.4.45 has been released New features are as follows: Block-level register allocation constraints; MMU plugin: structures' fields are listed from upper to lower bits. Block-level register allocation constraints This facility is aimed at overriding default settings written in the configuration file. MicroTESK 2.4.45 can be downloaded from here.