Month: June 2018

The MicroTESK team attended the conference “Computer-Aided Technologies in Applied Mathematics” (ICAM) held in Katun, Altai Region, Russia on June 4-8, 2018. We did two presentations on MicroTESK: Alexander Kamkin. Architecture-Level Microprocessor Verification Based on Formal Specifications; Alexander Protsenko & Andrei Tatarnikov. Automatic Test Template Generation Based on ISA Specifications.

The MicroTESK-for-RISC-V test program generator was demonstrated at the RISC-V Workshop held in Barcelona, Spain on May 7-10, 2018. https://riscv.org/2018/05/risc-v-workshop-in-barcelona-proceedings/ Alexander Kamkin (PM) and Andrei Tatarnikov (Team Lead) participated in the poster/demo session of the workshop. Here are links to the slides and video: Poster slides (pages 41 – 42): https://content.riscv.org/wp-content/uploads/2018/05/Barcelona-Workshop-Poster-Session-Slides.pdf Poster announcement (time 20:32 – 22:07): https://www.youtube.com/watch?v=ylTA63vPHYU The next RISC-V workshop will take place in Chennai on July 18-19, 2018 at the Indian Institute of Technology Madras.