Year: 2018

MicroTESK framework and machine-readable specifications of the RISC-V ISA were presented at RISC-V Summit held in Santa Clara, CA on December 3-6, 2018 and Workshop on Microprocessor/SoC Test, Security & Verification (MTV) held in Austin, TX on December 10-11, 2018. We reviewed MicroTESK for RISC-V and discussed a couple of its applications: test program generation and binary code verification. RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Each year, the RISC-V Foundation hosts global events to bring the expansive ecosystem together to discuss current and prospective RISC-V projects and implementations, as well as collectively drive the future evolution of the ISA forward. This was the first-ever RISC-V Summit with 1000+ registrants from 20 countries around the globe, 29 exhibitors, and…

MicroTESK was presented at the Technology Exhibition of the ISPRAS OPEN Conference held in Moscow on November 22-23, 2018. ISPRAS Open is an annual event organized by Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISPRAS). This year's conference was dedicated to the 70th anniversary of Russian Computer Science. On June 29, 1948, the Council of Ministers of the USSR issued the Decree №2369 on organization of Institute of Precision Mechanics and Computer Engineering (IPM and CE) of the Academy of Sciences of the USSR. On December 4, 1948, Isaak Brook, a corresponding member of the Academy of Sciences of the USSR, and his team received a certificate №10475 for invention of the electronic computing machine. On December 17, 1948, the Council of Ministers of the USSR…

MicroTESK 2.4.44 has been released New features are as follows: support for sections stored in separate files (useful for boot generation); decoder generator improvements: decode attribute and bit selection in image. Sections stored in separate files There are supported sections stored in separate files (an argument :file has been introduced). That facility may be useful for boot generation. Decoder generator A primitive (mode or op) is allowed to specify a decode attribute describing how to construct the primitive's arguments from the temporary variables (this is a hint to the decoder generator). It is permitted to select bits of non-immediate arguments in the primitive's image. MicroTESK 2.4.44 can be downloaded from here.

MicroTESK was presented at the Design and Verification Conference (DVCon Europe) held in Munich, Germany on October 24-25, 2018. We reviewed the tool and demonstrated a new feature that allows automatically generating architecture validation suites. DVCon Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.  

MicroTESK will be presented at RISC-V Summit to be held in Santa Clara, CA on December 3-6, 2018. Join us and learn how the free and open RISC-V architecture is revolutionizing the silicon market and beyond!

The MicroTESK team attended the conference “Computer-Aided Technologies in Applied Mathematics” (ICAM) held in Katun, Altai Region, Russia on June 4-8, 2018. We did two presentations on MicroTESK: Alexander Kamkin. Architecture-Level Microprocessor Verification Based on Formal Specifications; Alexander Protsenko & Andrei Tatarnikov. Automatic Test Template Generation Based on ISA Specifications.

The MicroTESK-for-RISC-V test program generator was demonstrated at the RISC-V Workshop held in Barcelona, Spain on May 7-10, 2018. https://riscv.org/2018/05/risc-v-workshop-in-barcelona-proceedings/ Alexander Kamkin (PM) and Andrei Tatarnikov (Team Lead) participated in the poster/demo session of the workshop. Here are links to the slides and video: Poster slides (pages 41 – 42): https://content.riscv.org/wp-content/uploads/2018/05/Barcelona-Workshop-Poster-Session-Slides.pdf Poster announcement (time 20:32 – 22:07): https://www.youtube.com/watch?v=ylTA63vPHYU The next RISC-V workshop will take place in Chennai on July 18-19, 2018 at the Indian Institute of Technology Madras.