Year: 2017

MicroTESK was presented at the Microprocessor/SoC Test, Security & Verification (MTV) held in Austin, TX on December 11-12, 2017. Mikhail Chupilko presented our work on maintaining ISA specifications in MicroTESK test program generator (introducing generic operations and revision constructs to nML specification language). The purpose of MTV is to bring researchers and practitioners from the fields of verification, security and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in security and verification and vice versa. This is the 18th edition of the MTV Workshop, a testament to its success in providing an ideal environment…

MicroTESK for RISC-V was presented at the RISC-V Developers Forum held in Moscow, Russia on December 7, 2017. The event was organized by SOVEL jointly with Syntacore, a Russian company specializing in RISC-V cores.

MicroTESK was presented in Taipei, Taiwan. On November 29, Alexander Kamkin, the MicroTESK PM, gave a lecture on architecture-level microprocessor verification at the National Taiwan University of Science and Technology (Taiwan Tech). He considered evolution of test program generators (TPGs), discussed approaches to TPG development automation, and outlined new trends in the area. On December 1, Andrei Tatarnikov, the MicroTESK Core team lead, made a presentation at the Workshop on RTL and High-Level Testing (WRTLT). His talk was about combining multiple TPG engines in the MicroTESK framework. Taiwan Tech was established in 1974 as the first and the best higher education institution of its kind of technological and vocational education system in Taiwan. WRTLT is to bring researchers and practitioners of VLSI testing from all over the world together to…

We are pleased to announce the first build of MicroTESK for RISC-V. The build has the following properties: nML specifications of 201 instructions (including pseudo ones); no MMU specification; sample test templates. Here is a link to the project: http://forge.ispras.ru/projects/microtesk-riscv

Trying to keep up with the times, we started MicroTESK for RISC-V, an open test program generator for the open instruction set architecture (ISA). Here is a link to the project: http://forge.ispras.ru/projects/microtesk-riscv. The first build is expected on the beginning of December. RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation (http://riscv.org).

We are pleased to inform you that MicroTESK has general support for ARMv8.2-A. The formal specifications have been updated: enhanced memory model with wider virtual and physical addresses (52 bits); 16-bit SIMD instructions and FP instructions; Reliability, Availability, and Serviceability (RAS); Statistical Profiling Extension (SPE). It required 70 new instructions, modification of some older ones, and update of the MMU description. The overall specifications include 1000+ instructions; their volume is almost 20 KLOC. ARMv8.2-A is a 64/32-bit architecture developed by ARM Holdings (arm.com).

Andrei Tatarnikov (MicroTESK Core Team Lead) defended his PhD thesis on MicroTESK at Ivannikov Institute for System Programming of the Russian Academy of Sciences (ISP RAS). The title is “Automated Construction of Test Program Generators for Microprocessors Based on Formal Specifications”. Congratulations!

The recent MicroTESK build (2.4.34) supports two nML extensions that ease developing and maintaining ISA specifications: templates and revisions. Templates allow defining families of operations whose operands differ only in their data types. To describe an operation in a generic way, the following constructs have been introduced: type_of, size_of, and is_type. Here is an example. op cmd_B(op1: BYTE, ...) ... op cmd_D(op1: DWORD, ...) action = { ... } Revisions allows enabling/disabling ISA elements (registers, operations, etc.) depending on the current ISA version. In the example below, the cmd_v2 operation is enabled only when the CPU_V2 revision is turned on. @rev(CPU_V2) op cmd_v2(rd: REG, rn: REG) To define different versions of the same ISA element, the @rev construct can be applied to the element attributes (syntax, action, etc.). Here comes an example.…